1. Field of the Invention
The present invention relates generally to memory sub-systems and, more specifically, to a technique for reducing CAS latency in a memory device.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In today's complex computer systems, speed, flexibility, and reliability in timing and control are issues typically considered by design engineers tasked with meeting customer requirements while implementing innovations which are constantly being developed for computer systems and their components. Computer systems typically include a plurality of memory devices which may be used to store programs and data and which may be accessible to other system components such as processors or peripheral devices. Each memory device has an associated latency period corresponding to an interval between the time that the memory device receives an access request and the time it delivers the requested data. This time interval between request receipt and data delivery is referred to as the “CAS latency.” Because different memory devices are designed with different CAS latencies, a memory controller may be tasked with coordinating the exchange of requests and data in the system between requesting devices and the memory device such that timing parameters, such as CAS latency, are considered to ensure that requests and data are not corrupted by overlapping requests and data.
Typically, memory devices are grouped together to form memory modules such as dual-inline memory modules (DIMM). Computer systems may incorporate numerous modules to increase the storage capacity of the system. Because CAS latency on the memory devices contained on each memory module may differ from one module to another, each memory module is generally checked at boot-up such that the various module and device specific parameters, such as CAS latency, may be conveyed to the memory controller. Thus, each memory module may include a device to convey information, such as size, speed, and voltage, to the memory controller. One such device is a serial presence detect (SPD) which makes it easier for the system BIOS to properly configure the system to fit the particular performance profiles of the devices on the corresponding memory module. An SPD device is typically an eight-pin serial chip which stores information about the memory module including, but not limited to, the module size, speed, voltage, drive strength, and the number of row and column addresses. At boot-up, the BIOS reads these parameters and automatically adjusts values in its chipset to maximize reliability and system performance. If timing parameters are not adjusted at boot-up, the system may produce more errors and/or operate at non-optimal speeds.
To provide design flexibility, memory devices are often configured such that certain parameters, such as CAS latency, may be selected at boot-up. In systems incorporating numerous memory modules, it may be advantageous to adjust the CAS latencies in each of the devices such that they are the same for each device rather than providing devices which may operate at different speeds due to varying CAS latency selection. By selecting a single CAS latency to be applied to each of the devices throughout the system, the memory controller design may be simplified and conflicts may be easier to manage. For example, in a given system, a user may insert two different memory modules, where one memory module may be capable of better (i.e., lower) CAS latency. It may be desirable to program the better performing memory module to react with the same CAS latency as the slower memory module to simplify controller design, since the controller design may be complicated by providing a mechanism for operating at different CAS latencies depending on which DIMM is accessed.
One mechanism for facilitating the selection of CAS latency in a system involves using mode registers. At boot-up, the memory controller reads the SPD device on each memory module. After determining the current system configuration and the slowest memory module, a mode register in each memory module is written with the desired CAS latency (here the CAS latency of the slowest module in the present system). Thus, the mode registers are set to define the actual CAS latency of each memory device. The present invention may address one or more of the problems set forth above.